In discrete-time systems, including analog to digital converters (ADCs), a voltage amplifier may be necessary to increase the signal swing for further processing. Traditional precision amplification techniques, including closed-loop amplifiers, become less viable in nanometer-scale processes due to reduced transistor intrinsic gain. Additionally, these devices generally consume static power, which becomes a larger percentage of overall power consumption as dynamic power decreases with further device scaling.
Recently, interest has grown in using dynamic amplifiers in discrete-time systems. These amplifiers consume no static power, allowing for increased power efficiency as devices scale. Additionally, these devices are generally constructed in open-loop configurations, which greatly reduce the gain requirements for the amplifier. However, these dynamic amplifiers suffer from their own limitations, including increased sensitivity to process variation and inaccurate gain.
Traditional precision amplification techniques, including closed-loop amplifiers, become less viable as complementary metal-oxide-semiconductor (CMOS) devices continue to scale to smaller sizes. In order to achieve the desired closed-loop gain in the presence of process variation, an open-loop gain many times larger than the desired gain is required. Nanometer-scale devices suffer from reduced intrinsic gain, which limits the maximum achievable open-loop gain.
Successive approximation register (SAR) ADCs are very popular for medium resolution (8-10 bits) applications because of their mostly digital architecture and high power efficiency. One drawback of this architecture is that the capacitive digital-to-analog converter (CDAC) size doubles with each additional bit. At higher resolutions, this can cause the reference energy and area to grow prohibitively large. Each additional bit also requires an additional comparison, which can limit the overall speed of the converter. One method to address these issues is to split the SAR into multiple pipelined stages. Pipelining allows the CDAC to be sized only according to sampling noise constraints and reduces the number of serial conversions per conversion cycle. The main drawback to this approach is the requirement of residue amplification between each stage. As noted above, traditional closed-loop residue amplifiers require large open-loop gains. In advanced processes, achieving a high gain is limited by small transistor intrinsic gain and reduced voltage supplies, which limits cascaded transistor stacks. Moreover, these amplifiers consume static power, which limits the power efficiency when compared to a standard single-stage SAR architecture.
Many recent works have proposed alternatives to traditional closed-loop residue amplifiers. One option is to perform open-loop residue amplification, greatly reducing the required amplifier gain. The drawback to this approach is increased amplifier non-linearity, which can require complex digital calibration (see B. Murmann and B. E. Boser, “A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification,” IEEE JSSC, vol. 38, no. 12, pp. 2040-2050, December 2003.) Even when linearization techniques are used to remove the calibration requirement as in (L. Yu, M. Miyahara, and A. Matsuzawa, “A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers,” in 2015 IEEE A-SSCC, November 2015, pp. 1-4), the amplifier still consumes static power. Other recent works have proposed using dynamic amplifiers, or integrators, for residue amplification. While integrator-based amplifiers are attractive because they achieve high power efficiency for a given input-referred noise, one drawback is that the maximum achievable gain is limited by the amplifier's component specifications, such as the ratio of select transistors' transconductance to respective transistor drain currents, i.e., transistor gm/ID, which is a measure of a transistor's efficiency in translating current to a transconductance (current gain). The allowable output common-mode voltage change, which is limited by the voltage supply, also affects maximum achievable gain. In some instances, this issue has been addressed by using a cascade to perform a double integration, which extends the allowable common-mode change, but the maximum gain is still limited. In B. Malki et al., “A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC,” in 2014 IEEE ESSCIRC, September 2014, pp. 215-218, the allowable common-mode change is extended by using both NMOS and PMOS transistors. In theory, multiple complementary phases can be used to achieve large gains, however the timing complexity is increased for each added phase. Another issue for most residue amplifier architectures is the mismatch between comparator and amplifier offsets. Offset mismatch both increases the amplifier's input swing and can cause over-ranging in later stage ADCs. Gain redundancy can relax the matching requirements to avoid over-ranging, but one bit of redundancy only allows for ½ LSB (Least Significant Bit) of offset mismatch between amplifier and comparator. These effects are especially harmful in dynamic-amplifier based pipelined SAR ADCs because 1) the linearity of dynamic amplifiers is generally much more sensitive to input swing than closed-loop amplifiers and 2) the first-stage resolution is generally high in order to maintain the SAR's power efficiency and limit the amplifier input swing, thus reducing the LSB size and the effectiveness of gain redundancy. In general, either large devices or offset calibration techniques must be used in order to meet the offset matching requirements.
One concept utilized in traditional SAR designs is the strong-arm latch. A strong arm latch, however, can only be used as a coarse amplifier. At the end of the strong-arm latch operation, one output will be at Vdd (positive supply) and one output will be at ground (negative supply). These latches, therefore, are really only suitable for use as voltage comparators or for amplifying low swing digital signals. Another important metric for precision amplifiers is the input-to-output linearity. Even with a well-controlled timing loop, the base strong-arm latch structure will have a gain that is highly dependent on the input voltage, which causes non-linearity in the input to output relationship.
The above noted limitations of traditional SAR designs are in addition to inherent problems in other traditional analog amplifier structures, where process scaling means increased difficulty in achieving precise gain.
Therefore, systems and methods are desired that overcome challenges in the art, some of which are described above.